TSMC Expands Cadence Tool Support in Integrated Signoff Flow by Adding Synthesis, Place and Route, and RC Extraction
April 12 2010 - 8:00AM
Marketwired
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global
electronic design innovation, today announced that it increases
tool support in TSMC's 65-nanometer Integrated Signoff Flow by
introducing RTL Compiler, EDI System, QRC Extraction and Encounter
Timing System for Signal Integrity into it. By following fully
validated, scripted and documented procedures within TSMC's
Integrated Signoff Flow, mutual customers can now establish an
end-to-end RTL-to-GDSII flow with predictable, shorter
time-to-volume for their 65-nanometer designs.
Global Unichip, a member of TSMC's Open Innovation Platform
eco-system, partnered with TSMC and Cadence in the beta test of
Integrated Signoff Flow. "Starting from 2008, we have successfully
taped out over 20 65-nanometer projects annually using
Cadence-based flow," said CC Hsieh, vice president of Design
Service at Global Unichip. "The collaboration with TSMC and Cadence
in Integrated Signoff Flow is a great opportunity to further
enhance our design flow efficiency and a critical step to bring
more success to our customers."
"To be successful in implementing their low-power,
high-performance SOC designs, our mutual customers need a proven
best-in-class methodology that allows them to get their design
ready for high volume production," said ST Juang, senior director
of design infrastructure marketing at TSMC. "In line with this, we
have worked closely with Cadence to expand EDA tool support in TSMC
Integrated Signoff Flow by integrating their implementation and RC
extraction capabilities into our flow."
"Cadence and TSMC have been working closely to ensure that
designers achieve their design goals as fast as possible when using
our solutions," said Dr. Chi-Ping Hsu, senior vice president of
Implementation R&D. "By qualifying EDI System and RTL Compiler,
our customers can now get the best of both worlds: large-scale,
high-performance physical synthesis and design closure capabilities
in EDI System and RTL compiler, backed by the world-class
manufacturing that results from using TSMC's Integrated Signoff
Flow."
About Cadence Cadence enables global
electronic design innovation and plays an essential role in the
creation of today's integrated circuits and electronics. Customers
use Cadence software and hardware, methodologies, and services to
design and verify advanced semiconductors, consumer electronics,
networking and telecommunications equipment, and computer systems.
The company is headquartered in San Jose, Calif., with sales
offices, design centers, and research facilities around the world
to serve the global electronics industry. More information about
the company, its products, and services is available at
www.cadence.com.
Cadence, the Cadence logo, Encounter and Virtuoso are all
registered trademarks of Cadence Design Systems, Inc. in the United
States and other countries. All other trademarks are the property
of their respective owners.
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For more information, please contact: Leslie Clavin Racepoint
Group 415-694-6717 lclavin@racepointgroup.com
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