Synplicity Announces Breakthrough ASIC Verification Solution
May 24 2007 - 8:00AM
Business Wire
Synplicity, Inc. (Nasdaq:SYNP), a leading supplier of software for
the design and verification of semiconductors, today announced its
revolutionary new Identify� Pro ASIC and ASSP verification
solution. The Identify Pro software, featuring Synplicity�s
TotalRecall� technology, provides designers with full visibility
into FPGA-based ASIC and ASSP prototypes enabling them to find, fix
and verify functional errors at speeds approaching that of the
final device. Identify Pro software improves the productivity of
existing verification methodologies, such as assertion-based
verification and simulation, resulting in a significantly reduced
overall verification time with improved verification coverage and
quality. Working with popular simulation tools, such as Synopsys�
VCS, (See today�s related announcement, �Synopsys and Synplicity
Establish Alliance to Advance High-Performance ASIC Verification�)
the Identify Pro solution automatically connects the prototype
hardware with an existing software simulation environment in a
transparent and seamless manner for comprehensive RTL code analysis
and debug. The Identify Pro software provides initialization of the
simulator and automatically creates a test bench from the actual
stimulus of the FPGA-based prototype, giving designers a
verification solution that is orders of magnitude faster in
performance than any other ASIC verification methodology. �Identify
Pro ushers in a new era of hardware-assisted verification and it is
one of the cornerstones of our ASIC and ASSP verification
strategy,� said Juergen Jaeger, senior director of ASIC
verification marketing at Synplicity. �As ASICs become bigger, more
costly and more software-centric, it is critical for the design
team to be able to effectively detect and analyze bugs that
otherwise would be missed until final silicon. The Identify Pro
software reduces this risk significantly by giving designers full
visibility into their design running at hardware speed in an
FPGA-based prototype. In case of an assertion, or other trigger,
the design, together with an automatically generated test bench, is
uploaded into a simulator for detailed debug and analysis. By
combining the visibility of a simulator with the speed of hardware,
the Identify Pro software provides a true breakthrough in ASIC
verification.� The Identify Pro software allows ASIC and ASSP
designers, using an FPGA-based prototype system, to functionally
debug their design at hardware speed, directly in their RTL source
code. This allows functional verification for RTL designs that is
up to 10,000 times faster than RTL simulators and enables the use
of �real-world� stimulus, making it an ideal verification platform
for applications like networking, audio, video, and all designs
with large amounts of software content. Used in conjunction with
Synplicity�s Synplify� Premier physical synthesis tool, the
Identify Pro software enables assertion synthesis into hardware and
assertion debug. The Identify Pro software offers the fastest
method of finding errors in an FPGA or ASIC prototype by using live
stimulus to quickly reach a trigger condition such as a functional
bug or assertion failure. By using advanced triggering
capabilities, including assertions that are inserted into the RTL
source code, design problems are found that could take a simulator
days or weeks to uncover. Once a functional bug or assertion
failure is found, the Identify Pro tool�s TotalRecall technology is
used to initialize a standard software simulator with all signal
and state values at a user-defined number of clock cycles prior to
the trigger being reached. The complete module state, along with a
test bench, is automatically exported to an RTL simulator where the
user can replay the sequence and diagnose bugs in the original RTL
source code. The Identify Pro product is ideal for ASIC
verification teams using FPGA hardware as it allows them to quickly
find functional errors in their design. With the coverage of
real-world data and the speed of real hardware, the Identify Pro
tool provides a comprehensive verification environment for finding,
fixing, and verifying functional errors in FPGA and ASIC designs.
Identify Pro Pricing and Availability The Identify Pro software,
featuring the TotalRecall technology, will be available for early
adopters in the third quarter of 2007. Prices range from $34,500
(USD)�for a one-year time-based license to $69,000 (USD) for a
perpetual, floating license. About Synplicity Synplicity�, Inc.
(Nasdaq:SYNP) is a leading supplier of innovative software
solutions that enable the rapid and effective design of
Programmable Logic Devices (FPGAs, PLDs and CPLDs) that serve a
wide range of communications, military/aerospace, consumer,
semiconductor, computer, and other electronic systems markets.
Synplicity's tools provide outstanding performance, cost and
time-to-market benefits by simplifying, improving and automating
key design planning, logic synthesis, physical synthesis and
verification functions for FPGA, FPGA-based ASIC verification, and
DSP designers. Synplicity is the number one supplier of FPGA
synthesis solutions and has been rated #1 in customer satisfaction
since 2004 in EE Times' Annual FPGA Customer Survey. Synplicity
products support industry-standard design languages (VHDL and
Verilog) and run on popular platforms. The company operates in over
20 facilities worldwide and is headquartered in Sunnyvale,
California. For more information visit http://www.synplicity.com.
Forward-Looking Statements This press release contains
forward-looking statements including, but not limited to,
statements regarding the performance, achievements, benefits and
market position of the Identify Pro software. In some cases, you
will be able to identify forward-looking statements by terminology
such as �may,� �will,� �should,� �expects,� �can,� �believes� or
the negative of these terms or other comparable terminology. These
statements are only predictions and involve known and unknown
risks, uncertainties and other factors that may cause the actual
results to differ materially from the forward-looking statements,
including the performance and benefits of Synplicity�s software
relative to relevant industry methods, standards, design flaws,
design difficulties or other problems with the Identify Pro
software, and the growth and changing technical requirements in the
FPGA and ASIC markets. For additional information and
considerations regarding the risks faced by Synplicity, see its
annual report on Form 10-K for the year ended December 31, 2006 and
Form 10-Q for the quarter ended March 31, 2007 as filed with the
Securities and Exchange Commission, as well as other periodic
reports filed with the SEC from time to time. Although Synplicity
believes that the expectations reflected in the forward-looking
statements are reasonable, Synplicity cannot guarantee the future
performance or achievements of its software. In addition, neither
Synplicity nor any other person assumes responsibility for the
accuracy or completeness of these forward-looking statements.
Synplicity disclaims any obligation to update information contained
in any forward-looking statement. Synplicity, Identify, and
Synplify are registered trademarks of Synplicity Inc. TotalRecall
is a trademark of Synplicity. All other names mentioned herein are
the trademarks or registered trademarks of their owners. SYB-0004
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