Synplicity Facilitates Open IP Encryption Methodology Standard; Methodology Enables Designers to Use Protected IP Throughout th
June 19 2006 - 8:00AM
Business Wire
Synplicity, Inc. (Nasdaq:SYNP), a leading supplier of software for
the design and verification of semiconductors, today announced that
the company has developed a free, non-proprietary IP encryption
flow that permits industry-wide interoperability. Synplicity is
offering this methodology to the EDA, IP and end-user communities
as a means to address the challenges designers face when using
protected IP in their design flows, which are often made up of
tools from several different EDA providers. The proposed
methodology supports tool interoperability and the underlying
technology allows IP providers and EDA vendors to deliver solutions
to their customers that provide the flexibility and security
necessary for an industry standard to emerge. Synplicity will host
a breakfast panel the morning of July 25 at the 2006 Design
Automation Conference in San Francisco to discuss this open IP
encryption flow and methodology. Panel members are comprised of
representatives from ARM, Cadence Design Systems, Lattice
Semiconductor, VSI Alliance (VSIA), Xilinx, and Synplicity. This
proposed IP encryption methodology, which is applicable to both
FPGA and ASIC design flows, should significantly simplify the
integration of IP for designers. Some EDA companies have attempted
to offer their own proprietary encryption schemes, but they did not
satisfy user needs because design flows typically consist of tools
from more than one EDA vendor. The proposed non-proprietary
methodology will allow IP vendors to create a single version of the
encrypted data that can be used by tools from multiple EDA vendors.
"The open IP encryption environment proposed by Synplicity will
facilitate the use of protected IP throughout the design flow, from
IP vendor to EDA vendor to silicon supplier," stated Gary Meyers,
president and CEO at Synplicity. "This methodology aims to create a
standard for encryption and decryption in electronic design flows,
which supports industry-wide interoperability, for any application
where FPGAs or ASICs are used." The methodology utilizes openly
available, well-tested, and government-approved encryption methods
combined with an encryption embedding mechanism proposed by Cadence
Design Systems for the next revision of IEEE 1364-2005. The
methodology permits IP vendors to choose how far encryption
persists through the design flow and includes the option of
encryption all the way to the semiconductor. This generic
cryptosystem approach combines symmetric encryption (also called
symmetric cipher, such as DES, 3DES and AES) with asymmetric
encryption (also called public key encryption, such as RSA). "A
standard mechanism for IP encryption will permit users to easily
employ encrypted IP with a wide variety of design flows," added
Meyers. "IP vendors will benefit from the protection of their
proprietary ideas while enjoying the benefits of its widespread
accessibility. EDA vendors will be able to offer tools that
accommodate the increasing variety of IP without having to deal
with hundreds of different protection mechanisms. In addition, the
semiconductor vendors, who often provide IP, will also benefit from
the shorter design times made possible by the extensive use of IP."
Several EDA vendors and IP providers have shown interest in this
open IP encryption methodology, including IP providers CAST and
PLDA, who stated: "Over thirteen years, we've seen various
mechanisms for protecting IP cores come and go, but Synplicity's
new integrated encryption approach is actually pretty slick," said
Hal Barbour, president of CAST, Inc. "It should simplify product
deliveries and sales evaluations for IP providers, and lead to
greater choice and flexibility for IP users. We're enthusiastic
about adopting it for CAST cores and expect that other IP firms and
more EDA companies will join in soon." "IP protection is a critical
concern for IP providers and users alike," said Callan Carpenter,
vice president of business development for PLDA, Inc. "Without it,
IP providers risk a complete loss of their investment, and users
are denied the benefits of a diverse and robust IP market. An
industry-standard solution such as this is ideal. Like the secure
socket layer on the Web, a standard solution will facilitate tool
flow and IP integration while still providing the industry with
great peace of mind." Synplicity to Host IP Encryption Breakfast
Panel During DAC 2006 To provide more information on the new
methodology, Synplicity will host a panel discussion during the
Design Automation Conference entitled, "An Industry Standard IP
Protection System for EDA Tool Flows." Panelists will include
representatives from ARM, Cadence Design Systems, Lattice
Semiconductor, Synplicity, VSIA, and Xilinx, and will be moderated
by Gabe Moretti, Gabe on EDA. The panel session will be held on
Tuesday, July 25, 2006 from 7:30 to 9:15 a.m. in Room 302 of the
Moscone Center. The panel session is open to all DAC attendees. To
register for DAC 2006 visit www.dac.com. About Synplicity
Synplicity(R) Inc. (Nasdaq:SYNP) is a leading supplier of
innovative software solutions that enable the rapid and effective
design of Programmable Logic Devices (FPGAs, PLDs and CPLDs) that
serve a wide range of communications, military/aerospace, consumer,
semiconductor, computer, and other electronic systems markets.
Synplicity's tools provide outstanding performance, cost and
time-to-market benefits by simplifying, improving and automating
key design planning, logic synthesis, physical synthesis and
verification functions for FPGA, FPGA-based ASIC verification, and
DSP designers. Synplicity is the number one supplier of FPGA
synthesis solutions and has been rated #1 in customer satisfaction
in 2004 and 2005 in EE Times' Annual FPGA Customer Survey.
Synplicity products support industry-standard design languages
(VHDL and Verilog) and run on popular platforms. The company
operates in over 20 facilities worldwide and is headquartered in
Sunnyvale, California. For more information visit
http://www.synplicity.com. Forward-Looking Statements This press
release contains forward-looking statements including, but not
limited to, statements regarding the performance and achievements
of the proposed open IP encryption methodology. In some cases, you
will be able to identify forward-looking statements by terminology
such as "may," "will," "should," "expects," "believes," "can" or
the negative of these terms or other comparable terminology. These
statements are only predictions and involve known and unknown
risks, uncertainties and other factors that may cause the forward
looking statements to differ materially, including the performance
and benefits of methodology, if such methodology is created, design
flaws, design difficulties or other problems with the proposed
methodology and changing technical requirements in the EDA
industry. For additional information and considerations regarding
the risks faced by Synplicity, see its annual report on Form 10-K
for the year ended December 31, 2005 as filed with the Securities
and Exchange Commission, as well as other periodic reports filed
with the SEC from time to time, including its quarterly reports on
Form 10-Q. Although Synplicity believes that the expectations
reflected in the forward-looking statements are reasonable,
Synplicity cannot guarantee the future performance or achievements
of the proposed methodology. In addition, neither Synplicity nor
any other person assumes responsibility for the accuracy or
completeness of these forward-looking statements. Synplicity
disclaims any obligation to update information contained in any
forward-looking statement. Synplicity is a registered trademark of
Synplicity Inc. All other brands or products are the trademarks or
registered trademarks of their respective owners.
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