Breker Verification Systems, whose product portfolio solves
challenges across the functional and system verification process
for large, complex semiconductors, today unwrapped its RISC-V
CoreAssurance™ and SoCReady™ SystemVIP providing a complete range
of automated tests for the entire RISC-V core and SoC verification
stack.
The first public demonstrations of RISC-V CoreAssurance and
SoCReady SystemVIP along with Breker’s Trek Test Suite Synthesis
portfolio will be held during the 61st Design Automation Conference
(DAC) June 24-26 and the RISC-V Summit Europe June 25-27.
“The verification of RISC-V cores remains a huge challenge and
we applaud the advent of RISC-V International’s certification
committee as a major step in the right direction,” remarks Adnan
Hamid, Breker’s Executive President and CTO. “This requires the
support of commercial-level verification suites that go well beyond
simplistic randomized instruction testing. Breker’s SystemVIP
synthesis platform enables advanced, rigorous verification to a
certification coverage level.”
The RISC-V Verification ChallengeRISC-V cores
require an extensive amount of verification, including capabilities
uncommon in general block test, necessary to achieve the quality
bar set by Arm and X86. RISC-V processor core and SoC verification
can be considered as a stack of verification tests starting with
basic instruction set architecture (ISA) compatibility to detailed
micro-architecture pipeline implementation stress tests and include
advanced integrity and integration testing to ensure reliable
system level operation and performance.
Once the basic ISA has been verified, a range of tests that
check the integrity of the core or SoC microarchitecture pipeline
implementation should be applied. Examples include load-store
stress testing, register hazards and memory hazards, exception
handling and complex interrupt patterns, varying privilege levels
and more. Coherency testing, paging and security (PMP) should also
be included. Finally, automated performance characterization is
used to identify operational bottlenecks.
Breker’s RISC-V CoreAssurance and SoCReady
SystemVIPBreker’s RISC-V CoreAssurance and SoCReady
SystemVIP provide the complete range of tests for the entire RISC-V
verification stack. Starting with randomized instruction generation
and microarchitectural scenarios, SystemVIP includes unique tests
that check all integrity levels, ensuring the smooth application of
the core into an SoC regardless of architecture and evaluating
possible performance and power bottlenecks and functional
issues.
SystemVIP can be extended for custom RISC-V instructions, fully
incorporating custom tests into the suite, cross multiplied with
other tests. All tests are self-checking and incorporate debug and
coverage analysis solutions. They may be seamlessly ported across
simulation, emulation, prototyping, post-silicon and virtual
platform environments.
Breker’s SystemVIP is based on synthesis technology that
amplifies generated tests to significantly improve coverage and bug
hunting. An AI technique called Planning Algorithms explores the
state space of the various scenarios starting with desired end
states and working backward to initial inputs, allowing for deep
sequential testing and precise execution analysis.
Built-in test cross combination combines various scenario
components in a multi-dimensional test array for all-inclusive
testing that digs into complex corner cases. Individual tests are
scheduled to execute concurrently further increasing pressure on
design components to reveal critical bottlenecks in design
architecture.
The Breker RISC-V SystemVIP has been deployed at multiple
companies working on RISC-V cores and SoCs that use home developed
or third-party RISC-V cores. They have proven to be instrumental in
the discovery of complex microarchitectural and system integrity
bugs, as well as ISA specification misunderstandings not found
using other verification means. On several occasions, bugs have
been discovered late in the development cycle, which would have
resulted in design failure.
Availability and PricingBreker’s RISC-V
CoreAssurance and SoCReady SystemVIP are available now as are its
Test Suite Synthesis solutions. Pricing is available upon
request.
For more information, visit the Breker website or email
info@brekersystems.com.
Breker at 61st Design Automation Conference
(DAC) and RISC-V SummitEUBreker will demonstrate its
RISC-V CoreAssurance, SoCReady SystemVIP and Trek Test Suite
Synthesis solutions at DAC Booth #2447 (second floor). It is a
Silver sponsor of the RISC-V Summit Europe and will take part in
the exhibition from Tuesday, June 25, through Thursday, June 27, at
the MOC Event Center in Munich, Germany.
At DAC, Dave Kelf, Breker’s CEO, will serve as a panelist during
the Accellera Luncheon Focused on Portable Stimulus Tuesday, June
25, from noon until 1:30 p.m. in Room 3016 at Moscone West.
Kelf will also participate in a DAC program panel “What is the
Future of Design Verification? UVM, PSS, Formal, VIP, AI &
Beyond,” Tuesday, June 25, from 3:30 p.m. until 5 p.m. in Moscone
West’s Room 2010 (second floor).
DAC will be held from Monday, June 24, through Wednesday, June
26, from 10 a.m. until 6 p.m. at Moscone West in San
Francisco. The RISC-V Summit Europe will be held Tuesday, June
25, through Thursday, June 27, at the MOC Event Center in Munich,
Germany.
To arrange a demonstration or a private meeting at either event,
send email to info@brekersystems.com.
DAC registration and RISC-V Summit Europe registration are
open.
About Breker Verification SystemsBreker
Verification Systems solves complex semiconductor challenges
across the functional verification process leveraging its SystemVIP
test suite library and test suite synthesis platform. Breker
solutions easily layer into existing UVM, software-driven and
post-silicon environments and operate across simulation, emulation,
prototyping, and post-silicon execution platforms. Its Trek family
is production-proven at leading semiconductor companies worldwide
and enables design managers and verification engineers to realize
measurable productivity gains, speed coverage closure and bug
hunting, and ease verification knowledge reuse. As a leader in the
development of the Accellera Portable Stimulus Standard (PSS),
privately held Breker has a reputation for dramatically reducing
verification schedules in advanced development environments. Case
studies that feature Altera (now Intel), Analog Devices, Broadcom,
IBM and other companies leveraging Breker’s solutions are available
on the Breker website.
Engage with Breker
at:Website: www.brekersystems.comTwitter: @BrekerSystemsLinkedIn: https://www.linkedin.com/company/breker-verification-systems/Facebook: https://www.facebook.com/BrekerSystems/
Trek, SystemUVM, CoreAssurance, SoCReady are trademarks of
Breker Verification Systems. Breker Verification Systems
acknowledges trademarks or registered trademarks of other
organizations for their respective products.
For more information, contact:Nanette CollinsPublic Relations
for Breker Verification Systemsnanette@nvc.com