SYNP Synplicity (MM)

Visit Synplicity in Its Booth #371 at the Design Automation Conference Offering attendees an advanced look at its future FPGA physical synthesis technology, Synplicity Inc. (Nasdaq:SYNP) a leading supplier of software for the design and verification of semiconductors, today announced it is demonstrating its unique graph-based physical synthesis technology in its booth at the Design Automation Conference in Anaheim, Calif. Synplicity's push-button, graph-based physical synthesis approach improves overall device performance while simultaneously delivering tight correlation between pre-route timing estimates and final post place-and-route results. Synplicity believes its new technology can provide from 5 to 20 percent better performance than logic synthesis alone. This technology also offers significantly faster timing closure by reducing the number of design iterations and eliminating the need for lengthy place & route runs. Attendees interested in viewing a demonstration of Synplicity's next-generation graph-based physical synthesis technology are welcome to visit Synplicity's booth at the Design Automation Conference. Synplicity is located in booth #371. "Synplicity is the first company to demonstrate for FPGA designers a single-pass physical synthesis solution that delivers simultaneous optimization, placement and routing," said Andy Haines, vice president of marketing at Synplicity. "With our graph-based physical synthesis technology, we continue to lead the FPGA synthesis market by innovating new technologies that enable faster timing closure and higher performing devices." Graph-Based Physical Synthesis Synplicity invented graph-based physical synthesis technology to enable a single-pass flow for 90nm FPGAs. Physical synthesis technology for FPGAs is fundamentally different than that of ASIC designs. The main difference is that close proximity of logic in an FPGA does not necessarily imply better timing due to its fixed routing structures. The key idea behind Synplicity's graph-based approach is that a detailed routing resource graph of pre-existing wires, switches and placement sites used for routing an FPGA, is created and used during physical synthesis. With this graph, optimization and placement are driven by wire delay and actual availability of resources, rather than measuring distance alone. Graph-based physical synthesis merges optimization, placement and routing to ensure critical paths of a design use the fastest routing resources available. This push-button physical synthesis flow generates a fully placed and physically optimized netlist ready for input to the FPGA vendor's routing tool. Based upon testing of approximately 200 designs to date, this technology has shown to provide a 5 to 20 percent timing improvement in a push-button flow. Physical re-timing may also be used to provide an additional performance boost over that obtained with graph-based physical synthesis alone. About Synplicity Synplicity(R) Inc. (Nasdaq:SYNP) is a leading supplier of innovative synthesis, verification and physical implementation software solutions that enable the rapid and effective design and verification of semiconductors. Synplicity's high-quality, high-performance tools significantly reduce costs and time-to-market for FPGA, structured/platform ASIC and cell-based/COT ASIC designers. The company's underlying Behavior Extracting Synthesis Technology(R) (BEST(TM)), which is embedded in its logical, physical and verification tools, and has led to Synplicity's top position in FPGA synthesis, now provides the same fast runtimes and quality of results to ASIC and COT customers. The company's fast, easy-to-use products support industry standard design languages (VHDL and Verilog) and run on popular platforms. Synplicity employs over 280 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, California. For more information visit http://www.synplicity.com. Forward-Looking Statements This press release contains forward-looking statements including, but not limited to, statements regarding Synplicity's development of its graph-based synthesis technology and the performance, achievements and benefits of graph-based synthesis. In some cases, you will be able to identify forward-looking statements by terminology such as "may," "will," "should," "expects," "believes" or the negative of these terms or other comparable terminology. These statements are only predictions and involve known and unknown risks, uncertainties and other factors that may cause the actual results to differ materially from the forward-looking statements, including the performance and benefits of Synplicity's graph-based synthesis technology or if and when such technology will become available. For additional information and considerations regarding the risks faced by Synplicity, see its annual report on Form 10-K for the year ended December 31, 2004 as filed with the Securities and Exchange Commission, as well as other periodic reports filed with the SEC from time to time, including its quarterly reports on Form 10-Q. Although Synplicity believes that the expectations reflected in the forward-looking statements are reasonable, Synplicity cannot guarantee the future performance or achievements of its software. In addition, neither Synplicity nor any other person assumes responsibility for the accuracy or completeness of these forward-looking statements. Synplicity disclaims any obligation to update information contained in any forward-looking statement. The specific features, functionality and release timing of any new technology as described in this press release remain at the sole discretion of Synplicity, Inc., and Synplicity does not make any warranty as to when or if such specific features, functionality or releases may occur. Synplicity and Behavior Extracting Synthesis Technology are registered trademarks of Synplicity Inc. BEST is a trademark of Synplicity Inc. All other names mentioned herein are the trademarks or registered trademarks of their owners.