TSMC Launches Integrated Sign-Off Flow to Shorten Design Cycle, Enhance Tape-Out Quality
April 21 2009 - 4:00AM
PR Newswire (US)
Open Innovation Platform Drives First Comprehensive and Executable
RTL To GDSII Design Flow HSINCHU, Taiwan, April 21
/PRNewswire-FirstCall/ -- Taiwan Semiconductor Manufacturing
Company, Ltd. (TSE:2330TSE:NYSE:TSE:TSM) today unveiled the first
foundry-specific Integrated Sign-Off Flow at its North American
Technology Symposium in San Jose, CA. The new flow is available now
for 65nm designs. Integrated Sign-Off Flow is an automated RTL to
GDSII chip implementation flow that tightly integrates all
process-specific items including pre-qualified library and IP,
selected EDA tools, production-quality flow, advanced design
methodology, and TSMC foundry technology files that have been
proven and refined over hundreds of applications. With embedded
TSMC design know-how and sign-off recommendations, the new flow
utilizes pre-qualified EDA toolsets from multiple vendors and
leverages industry-proven TSMC Reference Flow methodology. The
Integrated Sign-Off Flow, targeting initially at 65nm process node
with planned extensions into other process technology nodes,
supports advanced design techniques for low power and
design-for-manufacturability (DFM). It includes executable scripts
for complete flow automation and EDA tool queuing system support.
With validated libraries and IP, qualified EDA tools, full set of
proper technology files, and automated installation scripts,
Integrated Sign-Off Flow significantly shortens the time it
normally takes design team to set up the design environment and
flow before starting the design project. The built-in advanced
design methodology and proven sign-off scripts further shortens the
design cycle, and improves tape-out quality. "The ability to reduce
design setup effort and design cycle time clearly result in design
cost reduction, and this is one of the key objectives of the
recently launched TSMC Open Innovation Platform(TM)," explains ST
Juang, senior director of Design Infrastructure Marketing at TSMC.
"If we can lower design costs, we can help eliminate a major source
of profit erosion that impacts all ecosystem parties, including our
customers, our EDA partners and, of course, our own foundry
services. This Integrated Sign-Off Flow represents a highly
collaborative effort to increase reuse and reduce engineering
waste." Pricing and Availability The TSMC 65nm Integrated Sign-Off
Flow is available now in limited release and at no charge to
selective customers during Q2 2009. General release to other
customers is targeted for Q3 2009. Customers may access the
Integrated Sign-Off Flow at the TSMC Online customer design portal
http://online.tsmc.com/online/ or contact their local sales and
support representatives for details. About TSMC TSMC is the world's
largest dedicated semiconductor foundry, providing the industry's
leading process technology and the foundry's largest portfolio of
process-proven libraries, IP, design tools and reference flows. The
Company's total managed capacity in 2008 exceeded 9 million (8-inch
equivalent) wafers, including capacity from two advanced 12-inch -
GigaFabs(TM), four eight-inch fabs, one six-inch fab, as well as
TSMC's wholly owned subsidiaries, WaferTech and TSMC (China), and
its joint venture fab, SSMC. TSMC is the first foundry to provide
40nm production capabilities. Its corporate headquarters are in
Hsinchu, Taiwan. For more information about TSMC please visit
http://www.tsmc.com/. DATASOURCE: TSMC CONTACT: Wendy Matthews of
TSMC North America, +1-408-382-8030, or JH Tzeng of TSMC Corporate
Public Relations, 886-3-666-5028 Web Site: http://www.tsmc.com/
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