TSMCs
5-nanometer
technology offers our customers the
industrys most advanced logic process to address the exponentially growing demand for computing power driven by AI and 5G, said Cliff Hou, Vice President of Research & Development/Technology Development at TSMC.
5-nanometer
technology requires deeper design-technology
co-optimization.
Therefore, we collaborate seamlessly with our ecosystem partners to ensure we deliver
silicon-validated IP blocks and EDA tools ready for customer use. As always, we are committed to helping customers achieve first-time silicon success and faster
time-to-market.
5nm PDKs and EDA Tool Certifications
The latest 5nm PDKs are now available for production design, and include device symbols, Pcells, netlisting and techfiles to enable full design flow from
custom design, simulation, implementation, dummy fill, and extraction, to physical verification and signoff.
TSMC collaborated with design ecosystem
partners, including Cadence, Synopsys, Mentor Graphics, and ANSYS to certify full-line EDA tools through the TSMC OIP EDA Tool Certification Program. The core of the certification program covered silicon-centric EDA tool categories including
simulation, physical implementation (Custom Design, APR), timing signoff (STA, Transistor-level STA), Electromigration and IR drop (Gate-level and Transistor-level), physical verifications (DRC, LVS), to RC extractions (RCX). Through the
certification program, TSMC and EDA partners enabled design tools to support TSMC 5nm design rules, ensured required accuracy, and improved routability for optimized power, performance and area (PPA) for our customers to take full advantage of
TSMCs 5nm process technology.
5nm Design Flows
On top of tool certification, TSMC also added another layer of design flow certification with EDA partners using real designs to validate integrated tool flow
for both custom and digital designs. The flow certification focused on critical design implementation requirements using certified tools from respective EDA partners. Certification criteria cover tools feature readiness, robustness,
performance, correlation between implementation and
sign-off
tools, and design constraints compliance with real designs. Through the comprehensive tool and flow development, enhancement, and certification,
TSMC customers can implement their designs with optimized solutions, reduce design turn-around time, and strive for first-time-working silicon using TSMCs 5nm process technology. In addition, TSMC also provided reference flows for both mobile
and high-performance computing (HPC) applications which address new design methodologies to improve design quality and efficiency.