Fujitsu Standardizes on Cadence DFM Technologies for 28nm ASIC and Mixed-Signal Designs
September 19 2011 - 7:00PM
Marketwired
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global
electronic design innovation, today announced that Fujitsu
Semiconductor Limited has adopted Cadence® signoff
design-for-manufacturing (DFM) technologies for its complex
28-nanometer ASIC and system-on-chip (SoC) mixed-signal designs.
Deploying the Cadence DFM offerings helps Fujitsu Semiconductor
engineers ensure high yield, predictability, and a faster path to
Silicon Realization for next-generation chips that will serve as
the brains of the company's advanced consumer electronics. The
Cadence end-to-end digital and analog flows for Silicon Realization
deliver DFM in-design technology within the Virtuoso® custom/analog
and Encounter® digital flows.
"After an extensive evaluation of all vendors in the market, we
selected the complete Cadence DFM set of technologies for our most
advanced ASIC and SoC designs," said Hiroshi Ikeda, director of the
System LSI Technology and Design Platform Development Department at
Fujitsu Semiconductor Limited. "The production-proven DFM
technology gives us confidence in our ability to manage the
complexity of advanced 28-nanometer effects in the fastest
turnaround time, with the highest quality of silicon. Also, the
seamless integration into the Cadence Virtuoso and Encounter flows
makes it very straightforward for our design teams to adopt and
fully leverage in their day-to-day work."
Following comprehensive benchmarking, Fujitsu Semiconductor
selected the Cadence Litho Physical Analyzer, Cadence CMP Predictor
and Cadence Litho Electrical Analyzer for 28-nanometer in-design
physical signoff and variability optimization for its ASIC and SoC
designs.
As process geometries shrink beyond 28 nanometers, the Cadence
DFM technologies enable Fujitsu Semiconductor to tackle the
essential tasks of accurately modeling and predicting the impact of
physical and electrical variability (layout dependent effects) on
the yield and performance of a chip. Cadence in-design DFM signoff
tools enable engineers to analyze these impacts, and fix problems,
during digital and custom design implementation, rather than the
traditional -- and more costly and risky -- route of addressing DFM
signoff checks after the design is completed and ready to tape
out.
"We have been focusing our resources and working with leading
foundries to offer practical flows that enable companies like
Fujitsu Semiconductor to design complex chips with confidence that
they will meet ambitious goals of highest yield and quality," said
David Desharnais, group director, product marketing, Silicon
Realization at Cadence. "We are seeing our Cadence DFM
technologies, especially 'in-design' DFM, being aggressively
adopted and deployed by leading semiconductor companies because of
its multi-foundry certification and ability to efficiently and
effectively address this critical link in the design chain."
The Cadence Litho Physical Analyzer leverages proprietary,
foundational algorithms to provide near-linear scalability, thereby
providing blazing fast silicon convergence. The Cadence CMP
Predictor allows Fujitsu Semiconductor engineers to detect
topography variations of their manufacturing process early on via
extensive simulations. Fujitsu Semiconductor design teams use the
Cadence Litho Electrical Analyzer to identify and optimize their
libraries for layout-dependent effect variability early on,
therefore ensuring that their design meets their planned
performance metrics.
About Cadence
Cadence enables global electronic design innovation and plays an
essential role in the creation of today's integrated circuits and
electronics. Customers use Cadence software, hardware, IP, and
services to design and verify advanced semiconductors, consumer
electronics, networking and telecommunications equipment, and
computer systems. The company is headquartered in San Jose, Calif.,
with sales offices, design centers, and research facilities around
the world to serve the global electronics industry. More
information about the company, its products, and services is
available at www.cadence.com.
Cadence, Encounter, Virtuoso and the Cadence logo are registered
trademarks of Cadence Design Systems, Inc. in the United States and
other countries. All other trademarks are the property of their
respective owners.
Add to Digg Bookmark with del.icio.us Add to Newsvine
For more information, please contact: Dean Solov Cadence Design
Systems, Inc. 408-944-7226 dsolov@cadence.com
Cadence Design Systems (NASDAQ:CDNS)
Historical Stock Chart
From May 2024 to Jun 2024
Cadence Design Systems (NASDAQ:CDNS)
Historical Stock Chart
From Jun 2023 to Jun 2024