Cadence Extends the Open Verification Methodology Beyond SystemVerilog to Include SystemC and e Language Support
February 23 2009 - 8:00AM
Marketwired
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global
electronic design innovation, today announced the release of open
source libraries for e and SystemC languages to support the Open
Verification Methodology (OVM). Cadence� has contributed these
libraries, with accompanying usage examples and documentation, to
the OVM World Web site (www.ovmworld.org). The OVM was originally
developed for SystemVerilog; the Cadence contribution enables the
development of OVM-compliant verification components and
testbenches in any of the three IEEE-standard languages used for
verification and modeling: SystemVerilog, e, and SystemC.
"We are working with Cadence on several projects deploying the
OVM," said Suhas Belgal, senior verification manager at Magnum
Semiconductors. "The new e libraries will be a great benefit for
the verification community, since they will allow us to train all
of our engineers on a single methodology regardless of the language
they use. Also, being an SoC design house, it will enable us to use
VIPs from various IEEE standard languages under the OVM umbrella.
Our engineers will be able to integrate sophisticated verification
environments faster with the new libraries provided by
Cadence."
"We are delivering advanced verification technology in multiple
languages to our customers today," said Takahiro Kobori, senior
general manager, LSI Design and Development Division of OKI Network
LSI Co., Ltd. "This OVM multi-language new feature can help us to
implement one methodology while continuing to deliver verification
IP in each IEEE standard language required by our customers. The
new open source OVM e and SystemC libraries introduced by Cadence
will improve the design of verification environments throughout our
intellectual property."
The OVM was architected from the beginning with multi-language
verification in mind. By using transaction-level modeling (TLM)
channels as the basis for communication, OVM SystemVerilog
verification components can communicate easily with existing e and
SystemC components without changing those existing methodologies.
The new libraries allow verification engineers to develop new
components and testbenches in any of the three languages, using
corresponding library elements with the same methodology and reuse
guidelines.
"The reality is that to be globally effective, verification must
be a multi-language proposition," said Michal Siwinski, product
marketing group director for Verification Solutions at Cadence.
"Many of our customers use verification IP from other sources,
share verification components across projects, or engage in joint
development with other companies. Now, participants in this
ecosystem can use a single methodology with industry support for
interoperability, reuse, and scaling from block to system in all
three standard languages."
In addition to its contribution of the libraries, Cadence
supports the OVM with a broad range of products and services. The
OVM is fully integrated into the Cadence metric-driven verification
flow, which combines results from simulation, formal analysis,
hardware acceleration, and in-circuit emulation for a thorough
assessment of verification progress. Other unique offerings from
Cadence include a tremendously broad range of multi-language OVM
verification IP, builders to help create OVM-compliant verification
components, and services to aid in OVM startup and validation of
compliance to standard protocols.
Also today, Cadence announced the availability of a new
single-license model that grants verification teams access to the
extensive Cadence Incisive� Verification IP (VIP) Portfolio.
Availability
The e and SystemC library source code, examples, and
documentation are available immediately in the "Community
Contributions" area at http://www.ovmworld.org.
About the Open Verification Methodology
The Open Verification Methodology is the first open,
language-interoperable verification methodology in the industry. It
provides a methodology and accompanying library that allow users to
create modular, reusable verification environments in which
components communicate with each other via standard
transaction-level modeling interfaces. It also enables intra- and
inter-company reuse through a common methodology and classes for
virtual sequences and block-to-system reuse, and full integration
with other languages commonly used in production flows. The OVM is
supported by more than 50 companies offering training, services,
and products.
About Cadence
Cadence enables global electronic design innovation and plays an
essential role in the creation of today's integrated circuits and
electronics. Customers use Cadence software and hardware,
methodologies, and services to design and verify advanced
semiconductors, consumer electronics, networking and
telecommunications equipment, and computer systems. The company is
headquartered in San Jose, Calif., with sales offices, design
centers, and research facilities around the world to serve the
global electronics industry. More information about the company,
its products, and services is available at www.cadence.com.
Cadence, Incisive, and the Cadence logo are registered
trademarks of Cadence Design Systems, Inc. in the United States and
other countries. All other trademarks are the property of their
respective owners.
For more information, please contact: Dean Solov Cadence Design
Systems, Inc. 408-944-7226 dsolov@cadence.com
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