Fujitsu to Ship Initial Production Volumes of New Structured ASIC Built Using Cadence Encounter
August 01 2005 - 10:00AM
PR Newswire (US)
Fujitsu to Ship Initial Production Volumes of New Structured ASIC
Built Using Cadence Encounter AccelArray Giga Frame Used for
High-End Servers for Consumer Applications; Encounter Digital
Implementation Delivered Rapid Timing Closure SAN JOSE and
SUNNYVALE, Calif., Aug. 1 /PRNewswire/ -- Cadence Design Systems,
Inc. (NYSE:CDN) Nasdaq and Fujitsu Microelectronics America, Inc.
(FMA) today announced that FMA will ship initial production volumes
of a new, highly complex, structured ASIC using Cadence(R)
Encounter(TM) digital IC implementation in August. Encounter, which
was originally developed for standard ASICs, provided rapid timing
closure with signal integrity for optimal quality-of-silicon (QoS)
in the implementation phase of the design flow for FMA's
AccelArray(TM) family of structured ASICs. "We chose the Encounter
platform as the netlist handoff and for completion of physical
design such as the placement and routing, because it provided
excellent flexibility in implementing standard ASIC and structured
ASIC designs," said Noboru Yokota, senior director of engineering
at FMA. "This very complicated design, which FMA completed with
AccelArray Giga Frame, implements about 1.4 million instances of
cell." The design incorporates 3.5 million logic gates, 119
instances of 2RW SRAM (40bx512w), 33 instances of register file
(40bx32w) and 12-channel, 3.125G SERDES for high-end servers
developed for consumer applications. The design was completed with
low, non-recurring costs by using AccelArray Giga Frame. "We are
very happy with the success of our work with important customers
such as Fujitsu," said Wei-Jin Dai, platform vice president,
digital IC implementation at Cadence. "This is another example of
the Cadence Encounter platform's rapid route to complex,
high-performance SoC implementation." The Fujitsu AccelArray Giga
platform addresses the specific needs of mid-volume vertical
markets that require the performance of cell-based ASICs. These
platforms leverage Fujitsu's decades of ASIC design and
system-level expertise in the networking, storage networking,
next-generation consumer electronics and imaging markets. Giga
platforms reduce back-end physical design time such as DFT
insertion, power mesh, clock tree synthesis and simultaneous
switching output (SSO) analysis, all of which can consume a
considerable amount of time. The Giga platform offers up to 75Gbps
of full-duplex SERDES aggregated bandwidth by incorporating
pre-diffused universal G-PHY macro cells. SoC Encounter GPS
combines RTL synthesis, silicon virtual prototyping, and full-chip
implementation into a single system. It enables engineers to
synthesize to a flat virtual prototype implementation-including
full-chip, routed wires-right at the beginning of the design cycle.
With SoC Encounter GPS, engineers have an early, accurate view of
whether the design will meet its targets and be physically
realizable. Designers can then choose either to complete the final
implementation or to revisit the RTL design phase. About Fujitsu
Microelectronics America Fujitsu Microelectronics America, Inc.
(FMA) leads the industry in innovation. FMA provides high-quality,
reliable semiconductor products and services for the networking,
communications, automotive, security and other markets throughout
North and South America. For product information, visit the company
web site at http://us.fujitsu.com/micro/accelarray or please
address e-mail to . About Cadence Cadence is the world's largest
supplier of electronic design technologies and engineering
services. Cadence products and services are used to accelerate and
manage the design of semiconductors, computer systems, networking
equipment, telecommunications equipment, consumer electronics, and
other electronics based products. With approximately 4,900
employees and 2004 revenues of approximately $1.2 billion, Cadence
has sales offices, design centers, and research facilities around
the world. The company is headquartered in San Jose, Calif., and
trades on both the New York Stock Exchange and Nasdaq under the
symbol CDN. More information is available at
http://www.cadence.com/. NOTE: AccelArray is a trademark of Fujitsu
Limited. Cadence and the Cadence logo are registered trademarks and
Encounter is a trademark of Cadence Design Systems, Inc. All other
names mentioned herein are the trademarks or registered trademarks
of their owners. DATASOURCE: Fujitsu Microelectronics America, Inc.
CONTACT: Judy Erkanat of Cadence Design Systems, Inc.,
+1-408-894-2302, or ; or Emi Igarashi of Fujitsu Microelectronics
America, Inc., +1-408-737-5647, or ; or Dick Davies of Mindspring,
+1-415-777-4161, or Web site: http://www.cadence.com/ Web site:
http://www.fma.fujitsu.com/
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