MOUNTAIN VIEW, Calif.,
May 26, 2021 /PRNewswire/ --
Highlights of this Announcement:
- Synopsys design solutions certified for the latest version of
TSMC's 3nm process technology DRM and SPICE models
- Synopsys and TSMC have collaborated on advanced design
enablement using Synopsys' Fusion Design Platform and Custom Design
Platform so mutual customers can realize maximum PPA benefits from
TSMC's advanced process technologies
- Reference methodology benefits already validated across
mutual-customer designs, increasing number of successful
tapeouts
Synopsys, Inc. (Nasdaq: SNPS) today announced that
TSMC has certified Synopsys' digital and custom design solutions
based on TSMC's latest design-rule manual (DRM) and process design
kits for its advanced 3-nanometer (nm) process technology. This
certification results from extensive, multi-year collaboration to
deliver co-optimized tools, flows and methodologies that enable
customers to achieve the process' maximum entitlement of power,
performance and area (PPA), accelerating the next generation of
innovations in high-performance computing (HPC), mobile, 5G and AI
chip designs. To learn more about Synopsys' certified solutions,
the numerous test chips already completed at these nodes, how to
deploy Synopsys' design platforms and more, visit Synopsys' booth
during the TSMC 2021 Online Tech Symposium on June 1-2.
"TSMC's leading-edge technology required new levels of EDA
collaboration and innovation to deliver on the high performance and
low-power goals of the 3nm process technology," said Suk Lee, vice president of the Design
Infrastructure Management Division at TSMC. "Our long-term
collaboration with Synopsys has helped accelerate access to, and
the maximization of the benefits from, TSMC's latest process
offering. We will continue to work closely together to enable
next-generation designs for HPC, Mobile, 5G, and AI
applications."
Synopsys' highly integrated Fusion Design Platform is a critical
part of this successful advanced-node collaboration, delivering
comprehensive, full-flow design convergence and tight signoff
correlation for TSMC's 3nm technology. Synopsys' Fusion
Compiler™ and the IC Compiler™ ll
place-and-route product, achieve optimized timing
quality-of-results (QoR) through new global and detail-route
technology innovations. Full-flow, total-power optimization
advancements and concurrent-legalization-and-optimization
technology enable the achievement of the required total-power
profiles and the overall optimized PPA design metrics.
Other implementation technologies deployed as part of the 3nm
collaboration include support for advanced routing with coloring
and via-pillar consideration and innovative flip-flop optimization
that aids both performance-focused and low-power designs.
Additionally, the Design Compiler® NXT synthesis
product, a key component of the Fusion Design Platform, has been
enhanced to provide a more convergent design flow through tighter
timing correlation to IC Compiler II, benefiting all designs
targeting the N3 process.
Synopsys' 3nm collaboration with TSMC also includes
PrimeTime® support for low-voltage variation and
supports TSMC's placement rules to enable convergent ECO closure
during both implementation and signoff. Synopsys' PrimePower
supports 3nm physical rules for power signoff, including leakage
and dynamic power along with StarRC™ extraction-modeling
enhancements to deliver the needed accuracy.
Additional signoff solutions certified for TSMC 3nm technology
include NanoTime custom timing signoff, ESP custom equivalence
verification and QuickCap® NX parasitic field solver
solution. Synopsys' IC Validator ™ physical signoff has
been enhanced to support all advanced-process requirements,
including new dummy-fill features for improved density,
layout-dependent effects for layout-versus-schematic checking, and
enhanced delta-voltage rule-debug efficiency for DRC.
The Custom Compiler™ design and layout solution, part
of the Synopsys Custom Design Platform, delivers improved
productivity to designers using TSMC advanced process technologies.
Numerous enhancements to Custom Compiler, validated by early 3nm
users including the Synopsys DesignWare IP team, reduce the effort
to meet 3nm technology requirements. The Synopsys
PrimeSim™ HSPICE®,
PrimeSim™ SPICE, PrimeSim™ Pro and
PrimeSim™ XA simulators, as part of the
PrimeSim™ Continuum solution, deliver improved
turnaround time for TSMC 3nm designs and provide signoff coverage
for circuit simulation and reliability requirements.
"Both the ecosystem and our customers benefit from TSMC's and
Synopsys' close collaborations to push the achievable limits and
accelerate access to each new technology process," said Shankar
Krishnamoorthy, general manager and corporate staff for the Digital
Design Group at Synopsys. "Our latest digital and custom R&D
collaborations for the 3nm technology have delivered new levels of
technology innovation to overcome the challenges of the process and
thus open up a new chapter of opportunities for our mutual
customers to deliver on their advanced-product roadmaps in a timely
manner."
Synopsys technology files are available from TSMC for the 3nm
process technology. For a full list of the Synopsys digital
and custom platform solutions certified by TSMC, please visit:
www.synopsys.com/tsmc.
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to
Software™ partner for innovative companies developing
the electronic products and software applications we rely on every
day. As an S&P 500 company, Synopsys has a long history of
being a global leader in electronic design automation (EDA) and
semiconductor IP and offers the industry's broadest portfolio of
application security testing tools and services. Whether you're a
system-on-chip (SoC) designer creating advanced semiconductors, or
a software developer writing more secure, high-quality code,
Synopsys has the solutions needed to deliver innovative products.
Learn more at www.synopsys.com.
Editorial Contact:
Simone Souza
Synopsys, Inc.
650-584-6454
simone@synopsys.com
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SOURCE Synopsys, Inc.