Cadence Collaborates with Arm to Accelerate Hyperscale Computing and 5G Communications SoC Development
April 27 2021 - 10:05AM
Business Wire
Highlights:
- Latest collaboration builds upon previous successes where
leading server customers reached silicon on 7nm using the
previous-generation Arm Neoverse N1 platform and Cadence tools
- Cadence optimized its RTL-to-GDS digital full flow and
delivered corresponding 5nm and 7nm RAKs for Arm Neoverse V1 and
Neoverse N2 platforms, enabling designers to get to market
faster
- Cadence’s verification full flow enables Neoverse V1 and
Neoverse N2 platform users to achieve highest verification
throughput and preparedness for Arm SystemReady compliance
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that
it is expanding its collaboration with Arm to speed hyperscale
computing and 5G communications SoC development using Cadence®
tools and the new Arm® Neoverse™ V1 and Neoverse N2 platforms. To
build upon previous silicon successes where leading customers used
the first-generation Arm Neoverse N1 platform and Cadence digital
and verification tools on 7nm process technologies, Cadence
optimized its digital and verification full flows to drive adoption
of these latest platforms. Cadence also delivered comprehensive 5nm
and 7nm RTL-to-GDS digital flow Rapid Adoption Kits (RAKs) to help
customers optimize power, performance and area (PPA) goals and
improve productivity.
To learn more about the Arm-based solutions from Cadence, visit
www.cadence.com/go/cadencearmsols.
Digital Full Flow and RAKs
The integrated digital full flow from Cadence has been proven on
a 5nm, 4GHz Neoverse V1 implementation, delivering cutting-edge
performance—a key capability of the Neoverse platforms. Customers
working on advanced-node designs, including 3D-IC chiplets, can use
the new Cadence 5nm and 7nm RAKs to implement data center
server-class CPUs more efficiently and speed time to tapeout. The
complete Cadence RTL-to-GDS RAKs include the Genus™ Synthesis
Solution, Modus DFT Software Solution, Innovus™ Implementation
System, Quantus™ Extraction Solution, Tempus™ Timing Signoff
Solution and ECO Option, Voltus™ IC Power Integrity Solution,
Conformal® Equivalence Checking and Conformal Low Power.
The digital full flow provides some key features to speed the
delivery of 5nm and 7nm server-class designs, including:
- Cadence iSpatial technology, which provides an integrated,
predictable implementation flow for faster design closure
- Integrated Tempus timing and Voltus IR analysis for true power
integrity-driven timing signoff and optimization, which enables
designers to deliver more reliable devices
- The Tempus ECO Option offers signoff-accurate final design
closure using path-based optimization to achieve optimal PPA
Verification Full Flow and Engines
In addition to benefiting from Cadence’s proven 5nm, 4GHz
digital full flow, companies building Arm Neoverse-based SoCs can
achieve the highest SoC-level verification throughput by leveraging
Cadence’s verification full flow. In particular, the Cadence System
VIP solution has been enhanced with checkers, verification plans
and traffic generators to verify Arm Neoverse-based SoC coherency,
performance and Arm SystemReady compliance. All Cadence
verification engines, comprising Xcelium™ Logic Simulation,
Palladium® Z1 Emulation, Protium™ X1 Prototyping and JasperGold®
Formal Verification, are leveraged by these System VIP extensions
to deliver a comprehensive SoC-level verification flow for Arm
Neoverse-based SoCs.
“The modern infrastructure requires greater performance and
power efficiency to manage next-generation high-performance
computing and cloud-to-edge workloads,” said Chris Bergey, senior
vice president and general manager, Infrastructure Line of
Business, Arm. “By working with Cadence to optimize its digital and
verification full flows for Arm Neoverse-based solutions, our
customers can develop industry-leading products with optimal
PPA.”
“Arm and Cadence have a long history of collaborating on Arm IP
development, with the Neoverse V1 and Neoverse N2 platforms being
the most recent example,” said Dr. Chin-Chi Teng, senior vice
president and general manager in the Digital & Signoff Group at
Cadence. “By evaluating past customer successes with the Neoverse
N1 platform, we’ve successfully optimized the Cadence digital and
verification full flows to create high-frequency, low-power,
high-quality server-class designs using Arm’s newest infrastructure
platforms. With the new 5nm and 7nm RAKs and System VIP tools, our
data center and 5G infrastructure customers can rapidly deliver
innovative silicon solutions on schedule.”
The Cadence digital full flow provides customers with a fast
path to design closure and better predictability. The Cadence
verification full flow is comprised of best-in-class engines,
verification fabric technologies and solutions, which improve
verification throughput. The Cadence flows support the broader
Cadence Intelligent System Design™ strategy, enabling customers to
achieve design excellence.
About Cadence
Cadence is a pivotal leader in electronic design, building upon
more than 30 years of computational software expertise. The company
applies its underlying Intelligent System Design strategy to
deliver software, hardware and IP that turn design concepts into
reality. Cadence customers are the world’s most innovative
companies, delivering extraordinary electronic products from chips
to boards to systems for the most dynamic market applications,
including consumer, hyperscale computing, 5G communications,
automotive, mobile, aerospace, industrial and healthcare. For seven
years in a row, Fortune magazine has named Cadence one of the 100
Best Companies to Work For. Learn more at cadence.com.
© 2021 Cadence Design Systems, Inc. All rights reserved
worldwide. Cadence, the Cadence logo and the other Cadence marks
found at www.cadence.com/go/trademarks are trademarks or registered
trademarks of Cadence Design Systems, Inc. Arm is a registered
trademarks of Arm Limited (or its subsidiaries) in the US and/or
elsewhere. All other trademarks are the property of their
respective owners.
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