Rambus Delivers High-Speed SerDes Interface Solutions on GLOBALFOUNDRIES FX-14™ ASIC Platform for Data Center and Enterprise
October 12 2017 - 9:00AM
Business Wire
Suite of silicon-proven PHYs on 14nm LPP
process technology maximize performance and flexibility
Rambus Inc. (NASDAQ: RMBS), a leading provider of semiconductor
and IP products, today announced the availability of a suite of
silicon-proven, high-speed SerDes solutions including 16G MPSL
(multi-protocol serial link), 30G C2C (chip-to-chip) and 30G VSR
(very short reach) PHYs developed for GLOBALFOUNDRIES
high-performance FX-14™ ASIC platform. Built on the
GLOBALFOUNDRIES’ 14nm FinFET (14LPP) process technology, the Rambus
SerDes PHYs are optimized for power and area at peak bandwidth,
generating Ethernet speeds up to 100Gb and beyond for high-speed
wireline, wireless, 5G network infrastructure, high-performance
servers, storage, connectivity and compute applications.
“Data traffic and bandwidth demands have exploded, driving the
insatiable need for highly optimized, high-performance
semiconductor solutions,” said Luc Seraphin, senior vice president
and general manager of the Rambus Memory and Interfaces Division.
“Through our collaboration with GLOBALFOUNDRIES, Rambus is
delivering robust high-speed interface IP that enables innovative
chips and systems designed specifically for the Data Center and
Communications markets and helping GLOBALFOUNDRIES deliver value to
its customers through tested solutions.”
“Next-generation systems for cloud and communications must
deliver more performance and handle more complexity than ever
before,” said Kevin O’Buckley, vice president of product
development at GLOBALFOUNDRIES. “Working together with Rambus
enables us to provide ASIC solutions to our customers with a range
of high-speed SerDes interfaces that have been optimized for power
and area at peak bandwidth while maintaining complete compatibility
with industry standards.”
The Rambus SerDes PHYs include a Physical Media Attachment (PMA)
hard macro and Physical Coding Sub-layer with Built-in Self-Test
(PCS-BIST) soft macro. The PHYs can also be configured to multiple
channel widths and packaging options, which simplifies integration
and maximizes design flexibility.
For additional information on Rambus SerDes Interface Solutions,
please visit rambus.com/serdes.
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About Rambus Memory and Interfaces Division
The Rambus Memory and Interfaces Division develops products and
services that solve the power, performance, and capacity challenges
of the communications and data center computing
markets. Rambus enhanced standards-compatible and custom
memory and serial link solutions include chips, architectures,
memory and SerDes interfaces, IP validation tools, and system and
IC design services. Developed through our system-aware design
methodology, Rambus products deliver improved time-to-market and
first-time-right quality.
About Rambus Inc.
Rambus creates innovative hardware and software technologies,
driving advancements from the data center to the mobile edge. Our
chips, customizable IP cores, architecture licenses, tools,
software, services, training and innovations improve the
competitive advantage of our customers. We collaborate with the
industry, partnering with leading ASIC and SoC designers,
foundries, IP developers, EDA companies and validation labs. Our
products are integrated into tens of billions of devices and
systems, powering and securing diverse applications, including Big
Data, Internet of Things (IoT), mobile payments, and smart
ticketing. At Rambus, we are makers of better. For more
information, visit rambus.com.
Source: Rambus Inc.
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version on businesswire.com: http://www.businesswire.com/news/home/20171012005488/en/
SHIFT CommunicationsLeslie Clavin,
415-591-8440lclavin@shiftcomm.com
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