SAN JOSE, Calif., March 15, 2017 /PRNewswire/ -- Cadence Design
Systems, Inc. (NASDAQ: CDNS) today announced its collaboration with
TSMC to further advanced-node design innovation with TSMC's new
12nm FinFET Compact (12FFC) process technology. With
Cadence® digital and signoff solutions, custom/analog
solutions and IP, system-on-chip (SoC) designers can use the 12FFC
process to create emerging mid-range mobile and high-end consumer
applications that require optimal power, performance and area
(PPA). Cadence is actively working with customers on early
engagements with the 12FFC process.
In support of TSMC's new 12FFC process technology, Cadence
digital and signoff and custom/analog tools have achieved the
latest version of Design Rule Manual (DRM) certification for the
TSMC 12FFC process. A corresponding process design kit (PDK) is
also available for download. Additionally, Cadence has delivered a
library characterization tool flow and is developing IP for
customers migrating to the 12FFC process. To learn more about the
Cadence full-flow digital and signoff solutions, please visit
www.cadence.com/go/tsmc12ffcds. For information on the Cadence
custom/analog solutions, visit www.cadence.com/go/tsmc12ffcca. For
information on the Cadence IP solutions, please visit
www.cadence.com/go/tsmc12ffcip.
12FFC Digital, Signoff and Custom/Analog Tool
Certification
The Cadence digital and signoff and
custom/analog tools certified for the 12FFC process are as
follows:
- Innovus™ Implementation System: Enables
increased capacity and reduced turnaround time while supporting
TSMC's 12FFC design requirements, such as floorplanning, placement
and routing with integrated color-/pin-access/variability-aware
timing closure, and clock tree and power optimization
- Quantus™ QRC Extraction
Solution: Delivers on TSMC accuracy requirements for all
12FFC modeling features with required accuracy versus foundry
golden, offering multi-patterning and a built-in 3D extraction
capability
- Tempus™ Timing Signoff
Solution: Provides integrated, advanced process
calculation of delay and signal integrity effects, with static
timing analysis (STA) while achieving TSMC's rigorous accuracy
standards, including those at low-voltage operating conditions
- Voltus™ IC Power Integrity
Solution: Cell-level power integrity tool that supports
comprehensive electromigration and IR drop (EM/IR) design rules and
requirements while providing full-chip SoC power signoff
accuracy
- Voltus-Fi Custom Power Integrity
Solution: SPICE-level accurate tool that supports
comprehensive EM/IR design rules and requirements to analyze and
signoff analog, memory and custom digital IP blocks down to the
transistor device level
- Virtuoso® custom IC advanced-node
platform: Provides innovative, productivity-enhancing
implementation to verification flows, integrating electrical and
physical design checking that is correlated to the Cadence
TSMC-certified signoff platforms
- Spectre® simulation platform: Spectre
Circuit Simulator, Spectre Accelerated Parallel Simulator (APS) and
Spectre eXtensive Partitioning Simulator (XPS) deliver fast and
accurate circuit simulation with full support for advanced-node
device models with self-heating and reliability effects
- Physical Verification System: Includes advanced
technologies and rule decks to support design rule checks (DRCs),
layout versus schematic (LVS), advanced metal fill, yield-scoring,
voltage-dependent checks and in-design signoff
- Litho Electrical Analyzer: Allows layout-dependent
effect- (LDE-) aware re-simulation, layout analysis, matching
constraint checking, reporting on LDE contributions and the
generation of fixing guidelines from partial layout to accelerate
12FFC analog design convergence
The Cadence digital and signoff tools provide floorplanning,
placement, routing and extraction enhancements required for the
12FFC process technology. The Cadence custom/analog tools provide
underlying support and capabilities that enable designers to
improve productivity when compared with traditional, manual
approaches as well as fast, accurate verification of 12FFC design
performance and reliability.
12FFC Library Characterization Tool Flow Delivery
The
Cadence Virtuoso Liberate™ Characterization
Solution and the Virtuoso Variety™ Statistical
Characterization Solution have been validated to deliver
accurate Liberty libraries for the TSMC 12FFC process including
advanced timing, noise and power models. The solutions utilize
innovative methods to characterize Liberty Variation Format
(LVF) models, enabling process variation signoff for
low-voltage applications and the ability to create EM models
enabling signal EM optimizations and signoff.
12FFC IP Collaboration
Cadence has been working
closely with key 16FF+ and 16FFC customers for the past few years
and is beginning to work with customers adopting the 12FFC process
to develop next-generation applications processors for smartphones
and tablets as well as high-end consumer applications. Cadence is
currently migrating its flagship LPDDR4 PHY to the 12FFC process
node, targeting 4266Mbps so customers can reap the benefits of the
12FFC process. In addition, the Cadence LPDDR controller IP is
also 12FFC-ready. With a faster process and a new compact standard
cell library, customers using the 12FFC process can achieve better
chip area scaling and greater power savings.
"Our customers demand the highest quality design tools, IP and
process technologies, and they also value the flexibility that each
provides to help them reach the varying goals of each SoC project,"
said Dr. Anirudh Devgan, executive
vice president and general manager of the Digital & Signoff
Group and the System & Verification Group at Cadence. "TSMC's
new 12FFC process provides the FinFET process benefits customers
need in addition to performance and cost benefits. Through our work
with TSMC, our tools and IP can enable our mutual customers to
aggressively target their emerging markets using familiar tools and
flows."
"The introduction of our 12FFC process provides an ideal option
between our existing 16nm and 7nm processes for area- and
power-sensitive applications," said Suk
Lee, TSMC senior director, Design Infrastructure Marketing
Division. "Our ongoing collaboration with Cadence has resulted in
the timely delivery of a robust set of tools, flows and IP that
support this new process."
About Cadence
Cadence enables electronic systems and
semiconductor companies to create the innovative end products that
are transforming the way people live, work and play. Cadence's
software, hardware and semiconductor IP are used by customers to
deliver products to market faster—from semiconductors to printed
circuit boards to whole systems. The company's System Design
Enablement strategy helps customers develop differentiated products
in mobile, consumer, cloud datacenter, automotive, aerospace, IoT,
industrial and other market segments. Cadence is listed as one of
FORTUNE Magazine's 100 Best Companies to Work For. Learn more at
cadence.com.
© 2017 Cadence Design Systems, Inc. All rights reserved
worldwide. Cadence, the Cadence logo and the other Cadence marks
found at www.cadence.com/go/trademarks are trademarks
or registered trademarks of Cadence Design Systems, Inc. All other
trademarks are the property of their respective owners.
For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com
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SOURCE Cadence Design Systems, Inc.