SAN JOSE, Calif., Feb. 16, 2017 /PRNewswire/ -- Cadence Design
Systems, Inc. (NASDAQ: CDNS) will showcase the Cadence®
Verification Suite and its most recent innovations at DVCon 2017.
The event is being held February 27 to March
2, 2017 in San Jose,
Calif., with Cadence, a gold sponsor, in booth 702. To
register for the conference, visit https://dvcon.org.
WHAT: Join the Cadence speakers who will be participating
in the following presentations, posters, panels, and tutorials:
- Keynote: Tomorrow's Verification Today,
Tuesday, February 28 at 1:30 p.m., Dr. Anirudh
Devgan, senior vice president and general manager of the
Digital & Signoff Group (DSG) and the System & Verification
Group (SVG)
- Accellera Tutorial: Creating Portable Stimulus Models
with the Upcoming Accellera Standard, Monday, February 27 at 9:00 a.m., Sharon
Rosenberg, senior solutions architect
- Accellera Tutorial: Introducing IEEE 1800.2 – The Next Step
for UVM, Monday, February 27 at
2:00 p.m., Adam Sherer, product management group
director
- Poster: Mixed-Signal Verification Methodology to Verify USB
Type-C™, Tuesday, February
28 at 10:30 a.m., Varun R,
design engineer II
- Lunch Panel: Application-Specific Verification from
Edge Nodes Through Hubs, Networks, and Servers – Are the
Requirements All the Same?, Tuesday,
February 28 at 2:00 p.m.,
Frank Schirrmeister, senior product
management group director
- Presentation: Flexible Indirect Registers with UVM,
Tuesday, February 28 at 2:00 p.m., Uwe
Simm, software architect
- Panel: SystemVerilog Jinxed Half My Career – Where Do
We Go from Here?, Wednesday, March
1 at 1:30 p.m., Adam Sherer, product management group
director
- Cadence Tutorial: Reinventing SoC Verification – It Is
About Time, March 2 at
8:30 a.m., Larry Melling, product management director
- Cadence Tutorial: Optimizing IP Verification – Which
Engine? March 2 at
2:00 p.m., Pete Hardee, product management director
In addition, attendees will have the opportunity to hold
in-depth discussions on a variety of verification topics with
Cadence subject matter experts at the booth. Experts will be
available to discuss formal/static verification, parallel
simulation, emulation, FPGA-based prototyping, verification IP,
planning and metrics, debug, portable stimulus and many
more. For more information on Cadence activities at DVCon,
visit the Cadence events website at
www.cadence.com/go/DVCon2017.
WHEN: DVCon is scheduled for February 27 to March 2, 2017.
WHERE: Doubletree Hotel in San
Jose, Calif. Cadence is located in booth 702.
About Cadence
Cadence enables global electronic design innovation and plays an
essential role in the creation of today's integrated circuits and
electronics. Customers use Cadence software, hardware, IP and
services to design and verify advanced semiconductors, consumer
electronics, networking and telecommunications equipment, and
computer systems. The company is headquartered in San Jose, Calif., with sales offices, design
centers and research facilities around the world to serve the
global electronics industry. More information about the company,
its products and its services is available at www.cadence.com.
© 2017 Cadence Design Systems, Inc. All rights reserved
worldwide. Cadence, the Cadence logo and the other Cadence marks
found at www.cadence.com/go/trademarks are trademarks or registered
trademarks of Cadence Design Systems, Inc. All rights
reserved. All other trademarks are the property of their
respective owners.
For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com
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SOURCE Cadence Design Systems, Inc.