SAN JOSE, Calif., Nov. 14, 2016 /PRNewswire/ -- Cadence Design
Systems, Inc. (NASDAQ: CDNS) today announced that the
Cadence® Modus™ Test Solution now supports
the ARM® Memory Built-In Self Test (MBIST) interface,
enabling customers to efficiently create safety-critical
system-on-chip (SoC) designs using high-performance ARM processors.
To demonstrate the success of the collaboration, Cadence and ARM
have completed silicon validation using an ARM
Cortex®-A73 processor in conjunction with the Modus Test
Solution's automatic test pattern generation (ATPG) and diagnostic
capabilities.
Through Cadence's support of the ARM MBIST interface, customers
can deliver innovative SoC designs to market faster and with better
power, performance and area (PPA). For example, the Modus Test
Solution provides ARM MBIST interface users with the option for
programmable memory built-in self test (PMBIST) to use a single bus
to service multiple memories with one MBIST controller. The
solution utilizes the ARM MBIST interface to reduce the impact of
MBIST on critical timing paths to and from memories in functional
operation and for a higher quality at-speed test. Finally, the
Modus Test Solution provides a physical-to-logical mapping
capability, which reduces the need for manual, error-prone
work.
"The Cadence Modus Test Solution supports the ARM MBIST
interface and its many benefits," said Teresa McLaurin, fellow and director, technology
services group, ARM. "One feature is automation of the
physical-to-logical mapping capability that bridges the definition
of logical memories to a customer's unique physical memory
configuration, simplifying the task of integrating MBIST for ARM IP
in their products."
"We launched the Modus Test Solution earlier this year to
address escalating manufacturing test costs. Its patented 2D
Elastic Compression technology delivers up to 3X reduction in
manufacturing test costs," said Paul
Cunningham, vice president of research and development in
the Digital & Signoff Group at Cadence. "Since then, we've
continued to expand the Modus Test Solution's technical
capabilities, and by working with ARM, we're enabling customers to
easily incorporate ARM IP and Cadence flows in order to bring
competitive, safety-critical SoCs to market."
The Cadence Modus Test Solution is a comprehensive
next-generation physically aware design-for-test (DFT), ATPG and
silicon diagnostics tool. Using the Modus Test Solution, customers
can experience up to 3X reduction in test time using its patented
physically aware 2D Elastic Compression architecture, without any
impact on fault coverage or chip size. For more information on the
Modus Test Solution, please visit www.cadence.com/go/modusts.
About Cadence
Cadence enables global electronic design innovation and plays an
essential role in the creation of today's integrated circuits and
electronics. Customers use Cadence software, hardware, IP and
services to design and verify advanced semiconductors, consumer
electronics, networking and telecommunications equipment, and
computer systems. The company is headquartered in San Jose, Calif., with sales offices, design
centers and research facilities around the world to serve the
global electronics industry. More information about the company,
its products and its services is available at www.cadence.com.
© 2016 Cadence Design Systems, Inc. All rights reserved
worldwide. Cadence, the Cadence logo and the other Cadence marks
found at www.cadence.com/go/trademarks are trademarks or registered
trademarks of Cadence Design Systems, Inc. ARM and Cortex
are registered trademarks of ARM (or its subsidiaries) in the EU
and/or elsewhere. All rights reserved. All other trademarks
are the property of their respective owners.
For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com
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SOURCE Cadence Design Systems, Inc.