Palladium Z1 enables Fujitsu to predictably verify designs
larger than one billion gates
SAN JOSE, Calif., Oct. 24, 2016 /PRNewswire/ -- Cadence Design
Systems, Inc. (NASDAQ: CDNS) today announced that Fujitsu has
adopted the Cadence® Palladium® Z1
enterprise emulation platform for the development of the
ARM®v8-based Post-K computer. The Post-K computer is
the next-generation flagship supercomputer in Japan that reaches performance targets that
are a maximum of 100 times faster than the K computer, which is the
original 10-petaflop supercomputer that started full-scale
operation in 2012. After a rigorous multi-vendor selection process,
Fujitsu decided to use the Palladium Z1 enterprise emulation
platform exclusively for its advanced server and supercomputer
development.
With the Palladium Z1 platform's high compile speeds of greater
than 100 million gates per hour and its flexible job allocation,
Fujitsu benefits from iterative design turnaround of less than a
day for compile, allocation, execution and debug. With fast job
execution above 1MHz for billion-gate designs, efficient
hardware/software debug and virtualization capabilities, Fujitsu is
able to significantly enhance supercomputer development
productivity.
"In order to build a high-performance, scalable supercomputer
system, we needed a solution that could accommodate designs larger
than one billion gates, and the Palladium Z1 enterprise emulation
platform met all of our complex requirements," said Akira Kabemoto,
corporate executive officer and senior executive vice president,
Head of Service Platform Business at Fujitsu Limited. "The platform
is very easy to manage and scale which provides our engineering
teams with added confidence that they can deliver high-quality,
innovative designs to market within tight deadlines."
"Designing today's electronics, particularly those which are
state-of-the-art, increasingly requires a more comprehensive
verification approach," said Dr. Anirudh
Devgan, senior vice president and general manager of the
Digital & Signoff Group and the System & Verification Group
at Cadence. "The Cadence Palladium Z1 enterprise emulation platform
allows Fujitsu to improve their system-on-silicon verification and
hardware-software integration and optimization, ensuring high
reliability."
The Palladium Z1 platform, one of Cadence's core verification
engines, is the industry's first datacenter-class emulation system
that provides enterprise-level reliability and scalability with
lower total cost of ownership. The platform addresses the growing
market requirement for emulation technology that can be efficiently
utilized across global design teams to verify increasingly complex
systems on chip (SoCs). For more information, please visit
www.cadence.com/go/palladiumz1.
About Cadence
Cadence enables global electronic design
innovation and plays an essential role in the creation of today's
integrated circuits and electronics. Customers use Cadence
software, hardware, IP and services to design and verify advanced
semiconductors, consumer electronics, networking and
telecommunications equipment, and computer systems. The company is
headquartered in San Jose, Calif.,
with sales offices, design centers and research facilities around
the world to serve the global electronics industry. More
information about the company, its products and its services is
available at www.cadence.com.
© 2016 Cadence Design Systems, Inc. All rights reserved
worldwide. Cadence, the Cadence logo and the other Cadence marks
found at www.cadence.com/go/trademarks are trademarks or registered
trademarks of Cadence Design Systems, Inc. ARM is a
registered trademark of ARM (or its subsidiaries) in the EU and/or
elsewhere. All other trademarks are the property of their
respective owners.
For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com
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SOURCE Cadence Design Systems, Inc.